1. Field of the Invention
The present invention is directed to integrated circuit (IC) chips, and more particularly to revision identification (ID) number modification.
2. Related Art
An embodiment of the present invention provides a solution to a problem that plagues conventional integrated circuit (IC) chips. The problem is the hidden cost of additional metal mask layers when implementing a revision identification (ID) of the chip. This is a necessary requirement in order to inform a customer through software that the existing design of the chip has changed.
Conventionally, the revision ID is implemented as bits that are tied to either VDD (supply) or GND (ground) at any arbitrary layer of the chip. An additional metal layer is consumed by the revision ID when actual design changes are made on a different metal layer than where the revision ID was originally connected. For example, an additional metal layer will be consumed if the chip requires a logic fix on the metal 2 layer and the next revision ID bit needs to be tied to GND (ground) on the metal 4 layer. This will require two metal mask layer changes instead of just one on the metal 2 layer. Modification to the metal 4 layer is not necessary if the Revision ID could be changed in the metal 2 layer. In 0.18 μm technology, the cost per metal layer is high, and in 0.13 μm technology, the cost is even higher. Hence, the cost increases for finer pitch technology.
Additional costs also result from the engineering hours spent on the laborious layout task of minimizing the number of metal layers used to implement a change in the revision ID. For example, this task may consume a number of days just to save a metal mask. In addition, completely unique designs must be implemented for each chip in order to save mask costs. As a result, these designs cannot be re-used for other projects.
Significant cost savings for a company can be attained if one could completely eliminate the waste of mask layers and extra labor due to revision ID bit changes. This is a problem that affects a vast number of conventional IC chips.
Modifiable revision ID schemes exist, such as those described in U.S. Pat. Nos. 5,590,069 and 5,644,144, which are incorporated by reference herein in their entirety. The schemes disclosed in these two patents suffer from inefficient topological layouts.
Thus, what is needed is a method for manufacturing an integrated circuit structure that permits revision ID bit modifications to be contained only on mask layers where required logic changes are made, thereby reducing the cost of each chip design iteration, at minimal chip real-estate expense.